Research on the Key Technology of Circuit Design of CMOS Pixel Sensors for High-speed Imaging

Abstract

In this paper, the CMOS pixel sensor for high-speed imaging is taken as the research object, and the key technologies and future development paths are discussed. In this study, we first analyze the requirements of high-speed imaging circuit design and the circuit architecture classification of high-speed CMOS pixel sensors, and focus on the design of high-speed readout circuits, including column-level parallel ADC architecture, pixel-level digitization circuits, and mixed-signal processing techniques. This paper mainly introduces noise suppression and high dynamic range circuits, including related double sampling (CDS) circuit optimization, noise suppression of global shutter, and dynamic range extension circuits, focusing on low power consumption and reliability design, involving near-threshold voltage circuit design and dynamic power consumption management. Finally, this study discusses the necessity of process-circuit-algorithm co-optimization, emphasizes the synergistic relationship between process and circuit, and proposes a future technology roadmap to achieve key breakthroughs in circuit design, which will provide important reference and guidance for the development of high-speed imaging.