Advances and Progress in Asynchronous FIFO Design

Abstract

As integrated circuits continue to evolve, increasing the size and complexity of digital systems, in complex digital systems different modules may operate under different clock domains. For example, in a communication system, a data-receiving module and a data-processing module may be driven by separate clock sources. Therefore, an effective data caching mechanism is needed to coordinate data transfer between different clock domains. Asynchronous FIFOs fulfil this need by securely storing and transferring data between different clock domains, thereby reducing the risk of data loss and errors. By describing the design study of asynchronous FIFOs, this paper summarizes the features and advantages of asynchronous FIFOs in terms of sub-stability, creation of null-full signals, arbitrary adjustment of bit-width, and solving the problem of high latency through the analysis of several related research results, aiming to provide a reference for the further study and application of asynchronous FIFOs.